1. Field of the Invention
The present invention relates to an electronic circuit apparatus, for example, an optical information input apparatus such as a facsimile apparatus, an image reader, a digital copying machine, a laser recording apparatus, or a bar-code reader, a display apparatus, or a light-emitting element array and, more particularly, to an electronic circuit apparatus for generating pulse signals for selectively driving a large number of functional elements and a structure of the same.
2. Related Background Art
In recent years, a demand has arisen for miniaturization of the overall size of an electronic circuit apparatus. This tendency similarly applies to a photoelectric converting apparatus applicable to an optical information input unit of, e.g., a facsimile apparatus, a digital copying machine, or a laser recording apparatus, or to an apparatus for reading characters or images written on an original. For this reason, remarkable progress has been made in the development of a photoelectric converting apparatus which has a light-receiving surface of a size equal to or almost equal to the size of an original image to be reproduced, which is excellent in resolution, which can precisely read an original image, and which is compact, i.e., a photoelectric converting apparatus having a so-called elongated light-receiving surface.
On the other hand, a liquid-crystal display for displaying an image or an LED printer, for example, is required to have a large screen or elongated structure while maintaining its small size.
The electronic circuit apparatus as described above, however, has a serious problem in its internal signal processor.
In the case of a photoelectric converting apparatus, for example, a signal processor occupies a very large space compared to a photoelectric converter. Therefore, although the length of an optical path can be made very short by elongating the photoelectric converter, the above problem makes it difficult to satisfactorily use this advantage of miniaturization.
As a means for solving this problem, a system in which pixels (photoelectric converting elements) of the photoelectric converter are grouped into a plurality of blocks is generally adopted. In this system, these blocks are wired in a matrix manner, and the signal processor is operated in units of blocks.
A problem in this matrix wiring is that a bonding step is required to connect the photoelectric converting elements to the signal processor in order to extract signals, and this bonding step is increased extremely in number unless the photoelectric converting elements and the signal processor are integrated together.
As a method of solving this problem, an arrangement has been proposed in which switch units for transferring signals from individual photoelectric converting elements are formed by thin-film transistors (TFTs) and a shift register for sequentially driving these transfer TFTs time serially is formed on the same substrate (U.S. Pat. No. 4,461,956, Japanese Laid-Open Patent Application No. 56-138969). This method will be described below with reference to FIG. 1.
FIG. 1 shows an equivalent circuit diagram of the photoelectric converting apparatus described above. This photoelectric converting apparatus comprises an array of n photoelectric converting elements (PE1, PE2, . . . , PEN), capacitors (CE1, CE2, . . . , CEN) as storage means for storing output signals from the photoelectric converting elements PE, transistors (SW1, SW2, . . . , SWN) as transfer means for sequentially transferring the outputs from the photoelectric converting elements to an output terminal OUT, and a shift register (S11, . . . , S16, . . . , SN6) for allowing the transfer transistors to sequentially perform switching operations in a correct order.
Optical information incident on a light-receiving surface modulates the resistances of the photoelectric converting elements PE to change a current flowing from a power source V of the photoelectric converter into the storage capacitors CE. The electric charges stored in the storage capacitors CE are sequentially discharged from the output terminal OUT by switching on the N transfer transistors SW one by one in a predetermined order. That is, the incident optical information is time-serially extracted as the electric charges stored in the storage capacitors CE from the output terminal OUT during a time interval from one ON state to the next ON state of the transfer transistors SW.
Each stage of the shift register for driving one transfer transistor SW is constituted by six transistors. For example, a stage of the shift register for driving the transfer transistor SW1 is constituted by six transistors S11, S12, . . . , S16.
FIG. 2 shows a timing chart of the shift register and the transfer transistors SW.
Transfer clocks .o slashed..sub.1 and .o slashed..sub.2 have opposite phases. After N clocks .o slashed..sub.1 are counted, a transfer pulse is applied to a terminal IN. Each time two .o slashed..sub.1 pulses are counted, the transfer transistors SW are driven into an ON state in sequence in an order of SW1, SW2, . . . , SWN.
The photoelectric converting element PE is preferably a so-called ohmic sensor constituted by an electrode having ohmic junctions on both surfaces of a light acceptor layer. The transfer transistors and the transistors constituting the shift register are all thin-film transistors.
The light acceptor layer constituting the photoelectric converting element PE optimally consists of a semiconductor thin film, such as amorphous hydrogenated silicon (a-Si:H) or CdSe. This is so because these materials can function at low temperatures and allow a high degree of freedom in selection of the substrate.
If the transfer TFTs (thin-film transistors) SW and the TFTs S for the shift resistor consist of the same semiconductor, CdSe or a-Si:H, they can be formed through the same process, and short wiring can be designed because they can be formed close to each other.
As is generally known to those skilled in the art, however, these amorphous materials are inferior to single-crystal materials or polycrystalline materials in electrical characteristics, particularly the mobility of electrons and holes, which determines the speed of a transistor. Therefore, such an amorphous material poses problems in that it cannot completely transfer a signal within an assigned time when used as a transfer switch, that it cannot follow a high-frequency clock when used in a shift register, and that it cannot drive a transfer switch TFT for each bit at a necessary read rate. Of these problems, the problem as a transfer switch can be avoided by designing a TFT to have a high L/W (ratio of the channel length to width) so that its drive power is increased. Since, on the other hand, the speed of a shift register is determined essentially by the mobility of carriers, a simple delay in read rate per unit bit offers no problem in a photoelectric converting apparatus. However, current a-Si:H sometimes cannot meet a specification of reading out 1,728 bits (A4) in 5 msec as in a current G3 facsimile standard. That is, it is almost impossible to design a shift register for time-serially driving TFTs for individual bits in about 3 gsec by using current mass-producible a-Si:H.
Japanese Laid-Open Patent Application No. 59-185474 discloses an arrangement for solving the above problem, in which TFTs for a shift register consist of polysilicon (Poly-Si) having a higher mobility than that of a-Si:H.
In this conventional example, however, since Poly-Si itself has almost no function as a photoelectric converting element, a process of forming a-Si:H photoelectric converting elements is required in addition to the Poly-Si TFT process at 600.degree. C. or more. This increases the number of fabrication steps, and the results are a reduction in yield and an increase in fabrication cost.
A shift register of this type will be described below.
As a buffer circuit for generating and amplifying a pulse for selective driving for use in a shift register, a buffer circuit using a bootstrap effect as shown in FIG. 3 has been conventionally widely used.
Referring to FIG. 3, the gate electrode of a first MIS (metal insulator semiconductor) field-effect transistor (to be referred to as a MIST hereinafter) Tr1 is connected to an input terminal D, its first electrode (serving as a source or drain electrode) is connected to a power terminal B, and its second electrode (serving as a source or drain electrode) is connected to the gate electrode of a second MIST Tr2 (this node will be referred to as a node A for convenience). The first electrode of the second MIST Tr2 is connected to an output terminal Q, and its second electrode is connected to a terminal C for receiving a sync pulse signal. The first electrode of a third MIST Tr3 is connected to the node A, its second electrode is connected to a predetermined reference voltage (in this case, the ground potential), and its gate electrode is connected to a reset terminal R. The output terminal Q is connected to a load L to be driven. A stray capacitance Ca is present between the node A and the ground, and a capacitance Cb mainly formed between the gate electrode and the second electrode of the MIST Tr2 is present between the node A and the sync pulse input terminal C.
The operation of the conventional circuit having the above arrangement will be described below with reference to FIG. 3 and a timing chart of FIG. 4. The description will be made by taking an n-channel MIST as an example and using a positive logic. However, exactly the same description can be made for a p-channel MIST if the polarity of a voltage is inverted.
Assume that at time t0, the input terminal D, the reset terminal R, the output terminal Q, the sync pulse terminal C, and the node A are in state "0".
When the input terminal D changes to "1" at time t1, the MIST Tr1 is turned on to charge the capacitances Ca and Cb connected to the node A, and this raises the potential at the node A. At this time, since the first and second electrodes of the MIST Tr2, i.e., the terminal C and the output terminal Q remain at "0", the MIST Tr2 does not operate.
When the input terminal D changes to "0" at time t2, the MIST Tr1 is turned off, but the potential at the node A is kept at "1".
Subsequently, when a sync pulse is applied to the terminal C to raise the terminal C to "1" at time t3, the MIST Tr2 is turned on because a potential difference is produced between the first and second electrodes of the MIST Tr2 and the node A as its gate electrode is in state "1", and this raises the output terminal Q to "1". At this time, since the sync pulse is superposed on the potential at the node A by the bootstrap effect obtained by the capacitance Cb, the potential at the node A is increased to be higher than the potential held at the time t2. This makes it possible to raise the node A up to a voltage higher than the power source voltage. Therefore, the state "1" obtained at the output terminal Q can be a high voltage equal to the voltage of the sync pulse regardless of the threshold voltage of the MIST Tr2.
When the sync pulse goes to "0" at time t4, the MIST Tr2 is turned on in a direction opposite to that at the time t3 because the output terminal Q and the node A as its gate electrode remain at "1". As a result, a current flows from the output terminal Q to the terminal C to perform a reset operation by which the output terminal Q is lowered to "0". When a reset pulse is applied to the reset terminal R at time t5, the MIST Tr3 is turned on to reset the potential at the node A to the ground potential, "0". This reset operation prevents turning on of the MIST Tr2 even when the sync pulse rises to "1" at time t6. The MIST Tr2 operates only when the input terminal D is raised to "1" and in this manner functions as a buffer circuit.
The buffer circuit constituted by these MISTs consumes a small amount of a current unlike a buffer circuit shown in FIG. 5 in which two inverters are connected. This buffer circuit also has advantages that the size of the MIST Tr2 is relatively small, the output voltage can be as high as the voltage of the sync pulse, and the circuit is hardly influenced by variations in threshold voltage of the MIST Tr2. In addition, the circuit can be fabricated by a standard IC fabrication process and can also be fabricated relatively easily by a thin-film transistor fabrication process using a polycrystalline or amorphous semiconductor.
In FIG. 3, whether the output terminal Q goes to "0" or "1" when the sync pulse rises to "1" is determined in accordance with whether the potential at the node A is in state "0" or "1". If the potential at the node A is raised to "1" by, e.g., a leakage current (OFF current) of the MIST Tr1 or external noise although the input is "0", the circuit malfunctions. Therefore, it is necessary to reliably reset the node A t state "0".
FIG. 6 shows an example of a malfunction in which the output terminal Q rises to "1" although no input is applied to the input terminal D if the potential at the node A is raised by a leakage current of the MIST Tr1 to exceed the threshold voltage of the MIST Tr2 and a sync pulse is applied to the terminal C.
To stably keep the node A in state "0" , as shown in FIG. 7, a reset signal is kept applied to the reset terminal R to keep the MIST Tr3 on except when an input is applied to the input terminal D. In this method, the MIST Tr3 is generally almost always set on and is turned off only while an input is applied to the input terminal. This extremely increases the ON duty of the MIST Tr3. In a switching element, such as a MIST, in which an electric field is applied from a gate electrode to a semiconductor through an insulating film to form a channel, electrons, in the case of an n-channel element, are trapped in defects in the interface between the insulating film and the semiconductor film upon turning on of the element, and this shifts the threshold voltage to a value higher than its initial value. It is generally considered that the amount of this shift is proportional to the value of a gate voltage applied and its duty.
For this reason, the MIST Tr3 in the buffer circuit as described above easily causes such a shift in threshold voltage, and this raises the value of the threshold voltage. Then the MIST Tr3 cannot be turned on even when a reset signal is applied to the reset terminal R, and this makes it impossible to reliably reset the node A to "0", thereby causing a malfunction.
The shift in threshold voltage can be reduced by removing defects in the interface between the insulating film and the semiconductor film and those in the individual films. In recent years, therefore, the shift in threshold voltage caused by defects in films is considerably eliminated in a MIST using crystalline silicon, but problems sometimes arise along with a decrease in device size or the like. The problem of a shift in threshold voltage is still a serious problem in a thin-film transistor (to be referred to as a TFT hereinafter) using a material other than crystalline silicon, e.g., polysilicon or amorphous silicon (to be referred to as a-Si hereinafter).
FIG. 8 shows the relationship between the application time of a gate voltage of +12 V to the gate electrode of a TFT using a-Si and the shift amount in threshold voltage. As shown in FIG. 8, the threshold voltage which is initially 1 V is shifted to about 8 V when the gate voltage of +12 V is continuously applied for 250 hours. FIG. 9 shows the VGS-.sqroot.IDS characteristic of this TFT. Referring to FIG. 9, a solid line indicates the characteristic in the initial state, and a broken line indicates those obtained after an operation of 250 hours. The ON current for VGS=12 V obtained after an operation of 250 hours is decreased to 1/10 times or less that in the initial state. If a TFT having such a characteristic is used as the transistor Tr3 for resetting, although the TFT can normally perform a reset operation in its initial state, it cannot perform a satisfactory reset operation any longer as the operation time elapses, and finally causes a malfunction.
To prevent this malfunction, the gate voltage to be applied to the gate electrode may be raised to correspond to the shift in threshold voltage. If the gate voltage is set at a high value, the shift amount in threshold voltage is increased in proportion to the value. However, since the gate voltage and the shift amount in threshold voltage are in a linear proportional relationship, a large amount of an ON current can be constantly flowed if the gate voltage is set high.
That is, assuming that an ON current IDS is represented by Equation (1) and a shift amount AVTH in threshold voltage is represented by Equation (2), an ON current IDS' after a durability operation is given by Equation (3): EQU IDS=K(VGS-VTH).sup.2 (1) EQU .DELTA.VTH=.alpha.VGS (2) EQU IDS'=K{(1-.alpha.)VGS-VTH}.sup.2 (3)
where VGS is the gate voltage, K is a constant of proportion, VTH is the threshold voltage, and a is a constant of proportion representing the relationship between the shift amount in threshold voltage and the gate voltage.
An ON current IDS" after a durability operation performed by increasing the gate voltage by n times is given by Equation (4) by substituting VGS=nVGS into Equation (3): EQU IDS"=K{n(1-.alpha.)VGS-VTH}.sup.2 (4)
Since n&gt;1 and 0&lt;.alpha.&lt;1, IDS" is always larger than IDS'. In this manner, a large ON current can be flowed even after a durability operation if the gate voltage is raised, and this prevents a malfunction.
When the voltage to be applied to a circuit is raised, however, matching with other peripheral circuits may be degraded. It is also necessary to modify all the other peripheral circuits to correspond to the high voltage. Although another power source may be prepared for other circuits, the use of a plurality of power sources makes it very difficult to use the circuit.